Encapsulated conductive pillar and method of formation

ABSTRACT

The present invention provides an encapsulated 3-D conductive pillar and a method of formation thereof. Significant economic savings are achieved by filling a substantial portion of the volume of the pillar with a lesser expensive conductive material. Additionally, the encapsulated 3-D conductor pillar forms a suitable unreactive, oxygen-stable electrode for use with high-dielectric constant (HDC) materials as the encapsulating barrier layer metal provides a stable conductive interface between the HDC material and the encapsulated conductive material.

[0001] The invention generally relates to microelectronic structures,and more particularly, to an encapsulated three dimensional (3-D)conductive pillar suitable for use with high-dielectric constantmaterials and a method of formation thereof.

BACKGROUND OF THE INVENTION

[0002] Recent efforts for increasing capacitor density on an electronicsubstrate have focused on using high dielectric constant (HDC) materialsas the capacitor dielectric. Currently the most promising dielectricsare perovskites, a family of HDC materials recognized for theirexcellent charge storage properties. However, with some of these HDCmaterials (e.g. Ta₂O₅, TiO₂ and (Ba,Sr)TiO3 (BST), a good barrier layerwith effective diffusion and reaction barrier properties are requiredsince traditional microelectronic electrodes react adversely to suchmaterials, reducing their beneficial properties.

[0003] Accordingly, it is recognized in the industry that an oxygenstable electrode is required for use with such HDC materials. Exoticmaterials such as noble metals (Pt, Rh) have been considered as thenon-reactive electrode material. However, extravagant use of suchmaterials as an electrode material is prohibitive due to their cost.Additionally, at least a 1200 angstroms (Å) conductive layer is requiredin order to form a suitable 3-D conductive pillar of 0.46 microns by0.23 microns. Specifically for Pt, depositing such a conductive layertakes upwards of 15 minutes per wafer due to its very slow depositionrate using conventional deposition techniques. Such a long processingtime per wafer is undesirable due to the increase in productionexpenses.

[0004] Accordingly, there is a need for a 3-D conductive pillar which isboth suitable as an oxygen stable electrode for use with a HDC materialand economical to produce.

SUMMARY OF THE INVENTION

[0005] The present invention provides an encapsulated 3-D conductivepillar and a method of formation thereof. Significant economic savingsin material costs and production run times are achieved by filling asubstantial portion of the volume of the pillar with a less expensivematerial which can be deposited at a higher depositing rate.Additionally, the 3-D conductive pillar forms a suitable unreactive,oxygen-stable electrode for use with HDC materials as the encasingbarrier layer metal provides a stable conductive interface between theHDC material and the encapsulated conductive material.

[0006] In accordance with one aspect of the invention provided in afirst embodiment is a microelectronic structure comprising a substratelayer, a thin barrier layer metal on the substrate layer, and aconductive material encapsulated by the thin barrier layer metal.Provided in a second embodiment is a microelectronic capacitorcomprising an insulating substrate layer having a conductive plug. Themicroelectronic capacitor further includes a thin barrier layer metal onthe insulating substrate layer over the conductive plug, a conductivematerial encapsulated by the thin barrier layer metal, a dielectriclayer provided over the barrier layer metal, and a top electrode layerprovided over the dielectric layer. Provided in a third embodiment is amemory device having a microelectronic structure, the microelectronicstructure comprising a substrate layer, a thin barrier layer metal onthe substrate layer, and a conductive material encapsulated by the thinbarrier layer metal. Provided in a fourth embodiment is a memory devicehaving a capacitor, the capacitor comprising an insulating substratelayer having a conductive plug, a thin barrier layer metal on theinsulating substrate layer over the conductive plug, a conductivematerial encapsulated by the thin barrier layer metal, a dielectriclayer provided over the barrier layer metal, and a top electrode layerprovided over the dielectric layer. Provided in a fifth embodiment is acomputer system, the computer system includes a microelectronic device,the device comprises a substrate layer, a thin barrier layer metal onthe substrate layer, and a conductive material encapsulated by the thinbarrier layer metal. Provided in a sixth embodiment is a computersystem, the computer system includes a microelectronic device, thedevice comprises an insulating substrate layer having a conductive plug,a thin barrier layer metal on the insulating substrate layer over theconductive plug, a conductive material encapsulated by the thin barrierlayer metal, a dielectric layer provided over the barrier layer metal,and a top electrode layer provided over the dielectric layer.

[0007] In accordance with a second aspect of the present inventionprovided is a method of forming an encapsulated microelectronicstructure suitable for use with a high-dielectric constant material. Themethod comprises providing a substrate layer, forming a container havinga bottom and sidewalls from the substrate layer, and depositing a thinfirst layer of a barrier layer metal on the substrate layer covering atleast the bottom and sidewall of the container. The method furthercomprises depositing a conductive material on the barrier layer metalsubstantially completely filling the container, depositing a thin secondlayer of the barrier layer metal on the conductive material toencapsulate the conductive material in the container, and planarizingthe thin second layer of the barrier layer metal.

[0008] In accordance with the second aspect of the present inventionprovided is another method of forming an encapsulated microelectronicstructure suitable for use with a high-dielectric constant material. Themethod comprises providing a substrate layer having a surface, forming acontainer having a bottom and sidewall from the substrate layer, anddepositing a thin first layer of a barrier layer metal covering thebottom and sidewall of the container and the surface of the substrate.The method further includes depositing a conductive material coveringthe first layer of a barrier layer metal and completely filling thecontainer, removing a portion of the conductive material to expose anupper portion of the barrier layer metal provided on the sidewall of thefilled container, depositing a thin second layer of the barrier layermetal encapsulating the conductive material in the container, andplanarizing the thin second layer of the barrier layer metal.

[0009] In accordance with the second aspect of the present inventionprovided is method of forming a capacitor having an encapsulatedhigh-dielectric constant material. The method comprises providing asubstrate layer having a conductive plug, and forming a container havinga bottom and sidewall from the substrate layer, in which the conductiveplug is located at the bottom of the container. The method furtherincludes depositing a thin first layer of a barrier layer metal coveringthe bottom and sidewall of the container in which the conductive plugcontacts the first layer of the barrier layer metal, depositing aconductive material substantially completely filling the container, anddepositing a thin second layer of the barrier layer metal encapsulatingthe conductive material in the container. The method further includesplanarizing the thin second layer of the barrier layer metal, forming alayer of a high-dielectric constant material over the conductivematerial, and, forming a top electrode over the high-dielectric constantmaterial.

[0010] Other objects, features and advantages will appear more fully inthe course of the following discussion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIGS. 1-7 are cross-sectional views of a microelectronicstructure according to an embodiment of the present invention inprogressive steps of the fabrication of the same;

[0012] FIGS. 8-9 are cross-sectional views of a microelectroniccapacitor according to another embodiment of the present invention inprogressive steps of the fabrication of the same; and

[0013]FIG. 10 is a computer system comprised of a number ofmicroelectronic devices which may be fabricated with the embodiments ofthe present invention.

[0014] The same reference numerals refer to the same parts through thevarious figure embodiments.

DESCRIPTION OF THE INVENTION

[0015] The process steps and structures described below do not form acomplete process flow for manufacturing integrated circuits. The presentinvention can be practiced in conjunction with integrated circuitfabrication techniques currently used in the art, and only so much ofthe commonly practiced process steps are included as are necessary foran understanding of the present invention. The figures representingcross-sections of portions of an integrated circuit during fabricationare not drawn to scale, but instead are drawn so as to illustratepertinent features of the invention.

[0016] Referring to FIGS. 1-7, the fabrication of an encapsulated 3-Dconductor pillar 10 (FIG. 7) on a selected portion of a substrate 12 isdescribed in progressive steps. It should be understood that the term“substrate” is often used ambiguously in the art of integrated circuits.Often, the term “substrate” is used to refer to the underlying substrateof silicon, gallium arsenide or other semiconductive materials on whichan integrated circuit is fabricated. Additionally, the term “substrate”can also be used to refer to the incomplete portion or immediate layerof the integrated circuit on which a particular layer is formed. In thisspecification, the term “substrate” is used broadly to mean any layer onwhich a particular layer of interest is formed. Accordingly, thesubstrate layer may be any one selected from the group consisting ofsingle component semiconductor materials, compound semiconductormaterials, ceramic single crystals, ceramic poly-cystals, metals, andamorphous/glassy materials Furthermore, when functioning as aninsulating layer, the material of the substrate 12 is one selected fromthe group consisting of SiO₂, Si₃N₄, BSG, PSG, BPSG, MgO, CaO, CaF₂,Al₂O₃ or B₂O₃. In the embodiments described below the substrate 12 isBPSG. Moreover, as used herein, it should be understood that the term“on” refers to forming a material layer in contact with either theentire or a portion of the underlying substrate, and “over” refers toforming a material layer above either the entire or a portion of theunderlying substrate. Continuing, formed into an upper surface of thesubstrate 12 is a container 14 having a bottom 16 and sidewall 18.

[0017] Referring now to FIG. 2, on substrate 12 deposited is a thin film20 of a barrier layer metal 22. The term “thin” refers to a depositlayer of preferably up to about 200 Å. The barrier layer metal 22 is oneselected from the group consisting of platinum, palladium, ruthenium,indium, rhodium, osmium, silver, and gold, their oxides (e.g. RuO₂,IrO₂, Rh₂O₃, OsO₂, and PdO₂) and any metal which is effective as abarrier layer to prevent interdiffusion of silicon atoms andmetal/conductor atoms. The thin film 20 of the barrier layer metal 22 isdeposited on the substrate 12, uniformly covering the bottom 16 andsidewall 18 of the container 14 as illustrated. Preferably, chemicalvapor deposition (CVD) or sputtering techniques are utilized.Additionally, the substrate 12 may be heated to provide betterstability.

[0018] Now turning to FIG. 3, the barrier layer metal 22 is blanketedwith a conductive material 24. The conductive material is depositedpreferably by plasma enhanced chemical vapor deposition Or iondeposition sputtering, in order to substantially completely fill thecontainer 14. The term “substantially completely fill” refers to thecharacteristic of a feature, such as a container, trench or via, whichis filled substantially, if not completely with a conductive material.The conductive material 24 is one selected from the group consisting oftungsten (W), tungsten silicide (WSi_(x)), ruthenium (Ru), rutheniumoxide (RuOx), and silicon nitride (Si₃N₄).

[0019] As illustrated in FIG. 4, after depositing the conductivematerial 24 an in situ, highly directional cleaning is performed. Theconductive material 24 is cleaned with a fluorinated product, such asNF₃ clearing away an upper portion 26 of the filled container 14 andexposing the barrier layer 20 that surrounds the opening of the filledcontainer. Additionally, the upper portion 26 extends a predetermineddepth into the filled container 14.

[0020] As shown in FIG. 5, a second layer 28 of the barrier layer metal22 is deposited in the upper portion 26 of the filled container 14thereby encapsulating the conductive material 24 in the barrier layermetal 22. In this step, the second layer 28 of the barrier layer metal22 is preferably deposited by CVD or sputtering to a thickness ofpreferably about 200 Å.

[0021] To reveal the pillar 10 as shown in FIG. 7, the materialsurrounding the encapsulating barrier layer metal 22 of the conductivematerial 24 must be removed. To remove these materials, the barrierlayer metal 22 provided in the upper portion 26 of the container 14 isplanarized by any conventional planarizing technique including ChemicalMechanical Planarization (CMP), thereby forming the microelectronicstructure illustrated by FIG. 6. Next, anisotropic etching is utilizedto remove the remaining materials thereby exposing the sidewall 18 ofthe pillar 10 as illustrated in PIG. 7. It should be appreciated thatthe above described microelectronic structure is useful as a bottomelectrode in a microelectronic capacitor. The steps to complete amicroelectronic capacitor with the above described pillar 10 aredescribed with reference to FIGS. 8 and 9.

[0022] In FIG. 8, a dielectric layer 32 is formed over the pillar 10.Since the pillar 10 is serving as the bottom electrode in an integratedcircuit, typically a conductive plug 34 is provided at the bottom of thecontainer 14 by any suitable conventional method before depositing thebarrier layer metal 22 in the processes steps described above. Theconductive plug is a material selected from the group consisting of TiN,zirconium nitride titanium silicide, tantalum silicide, tungstensilicide, molybdenum silicide, nickel silicide, cobalt silicide,tantalum carbide, tantalum boride, polysilicon, germanium, W, Ta, Ti,Mo, TiW, boron carbide, and Cu and the like. As known, the conductiveplug 34 contacts other contact areas, such as a source/drain, providedin another substrate layer. Dielectric layer 32 is a high dielectricconstant dielectric, typically having a dielectric constant greater than50, wherein the exact nature of this layer will depend upon theapplication. An example of high dielectric constant material typicallyused is selected from the group consisting of perovskites such asbarium-strontium titanate (BST), Ta₂O₅, TiO₂, ferroelectrics such asPb(Zr,Ti)O₃, (Pb,La)(Zr,Ti)O₃, Nb doped PZT, doped PZT, Bi₄Ti₃O₁₂,SrBi₂(Ta,Nb)₂O₉, pyroelectrics, and high dielectric constant oxides.Dielectric layer 32 may extend over the entirety of the area of thesubstrate 12 thereby simplifying the process of fabricating theintegrated circuit, since a mask and a sequence of patterning steps maybe omitted. Alternatively, if the layer 32 is specifically patterned,the patterning is done in an area of the integrated circuit which issurrounded by insulator and in which no critical parts are located, andthus it can be done with much greater tolerances, which also simplifiesthe overall process.

[0023] A heat treatment is performed at an elevated temperature of about400° C. to about 900° C. for about 1 minute to 3 hours, wherein thetreatment preferably includes rapid thermal anneal (RTA) and/or furnaceanneal.

[0024] Next, as illustrated by FIG. 9, a top electrode layer 36 isformed, preferably by sputtering over the dielectric layer 32 tocomplete the microelectronic capacitor. The top electrode layer ispreferably platinum, or any other conventionally used material.Additional conventional layers may then be deposited over the topelectrode layer 36, such as a protective layer of tantalum, hafnium,tungsten, niobium and zirconium as is known. It should be appreciatedthat the dielectric layer 32 sandwiched between electrodes 10 and 36together form an electronic component which changes its electronic stateduring operation in a completed integrated circuit. This is in contrastto other dielectric layers, such as an interlayer dielectric, which doesnot change its electronic state during the operation of the integratedcircuit. Furthermore, although FIG. 8 shows the use of the pillar 10 asa bottom electrode in the microelectronic capacitor 30, the technique ofencapsulating a conductive material as illustrated in FIGS. 1-5, can beused with a conductor line as well. For example, copper or silverencapsulated in Al or Ta, or Ti, and the like. It is to be appreciatedthat the microelectronic structure formed by the illustrative processesof FIGS. 1-7 may be used in a computer system as part of its memorydevice or as part of its integrated circuitry. Additionally, themicroelectronic capacitor formed by the illustrated processes of FIGS.1-9, may be used in a computer system as part of its memory device orits integrated circuitry.

[0025]FIG. 10 is an illustration of a computer system 612 that can useand be used with embodiments of the present invention. As will beappreciated by those skilled in the art, the computer system 612 has anumber of microelectronic devices that include, for example, ROM 614,mass memory 616, peripheral devices, and I/O devices 620 incommunication with a microprocessor 622 via a data bus 624 or anothersuitable data communication path. These devices can be fabricatedaccording with the various embodiments of the present invention.

[0026] In a typical embodiment, the following ranges of layerthicknesses and sizes may be used. As will be appreciated by thosepersons skilled in the art, these numbers may be modified to suitvarious processing requirements. The size of the container thus has awidth ranging from preferably about 1500 Å to about 2000 Å, and a heightranging from preferably about 2000 Å to about 30000 Å. Accordingly, thedielectric layer 32 has a thickness of preferably about 30 Å, and thetop electrode layer a thickness of preferably about 500 Å.

[0027] Having thus described the present invention in detail and byreference to preferred embodiments thereof, it will be apparent thatmodifications and variations are possible without departing from thescope of the invention detailed in the appended claims.

What is claimed is:
 1. A microelectronic structure comprising: asubstrate layer; a thin barrier layer metal on said substrate layer; anda conductive material encapsulated by said thin barrier layer metal. 2.The microelectronic structure of claim I wherein said substrate layer isselected from the group consisting of single component semiconductormaterials, compound semiconductor materials, ceramic single crystals,ceramic poly-crystals, metals, and amorphous/glassy materials.
 3. Themicroelectronic structure of claim 1 wherein said thin barrier layermetal is selected from a group consisting of platinum, palladium,ruthenium, iridium, rhodium, osmium, silver, gold, RuO₂, IrO₂, Rh₂O₃,OsO₂, and PdO₂.
 4. The microelectronic structure of claim 1 wherein saidconductive material is selected from the group consisting of W, WSi_(x),Ru, RuOx, and Si₃N₄.
 5. The microelectronic structure of claim 1 adaptedfor use as an oxygen stable electrode with a high-dielectric constantmaterial.
 6. A microelectronic capacitor comprising: an insulatingsubstrate layer having a conductive plug; a thin barrier layer metal onsaid insulating substrate layer over said conductive plug; a conductivematerial encapsulated by said thin barrier layer metal; a dielectriclayer provided over said barrier layer metal; and a top electrode layerprovided over said dielectric layer.
 7. The microelectronic capacitor ofclaim 6, wherein said insulating substrate layer is selected from thegroup consisting of SiO₂, Si₃N₄, BSG, PSG, BPSG, MgO, CaO, CaF₂, Al₂O₃and B₂O₃.
 8. The microelectronic capacitor of claim 6, wherein saidconductive plug is selected from the group consisting of TiN, zirconiumnitride, titanium silicide, tantalum silicide, tungsten silicide,molybdenum silicide, nickel silicide, cobalt sulicide, tantalum carbide,tantalum boride, polysilicon, germanium, W, Ta, Ti, Mo, TiW, boroncarbide, and Cu.
 9. The microelectronic capacitor of claim 6, whereinsaid thin barrier layer metal is selected from the group consisting ofplatinum, palladium, ruthenium, iridium, rhodium, osmium, silver, gold,RuO₂, IrO₂, Rh₂O₃, OsO₂, and PdO₂.
 10. The microelectronic capacitor ofclaim 6, wherein said conductive material is selected from the groupconsisting of W, WSi_(x), Ru, RuOx, and Si₃N₄.
 11. The microelectroniccapacitor of claim 6, wherein said top electrode layer is platinum. 12.A method of forming an encapsulated microelectronic structure suitablefor use with a high-dielectric constant material, the method comprising:providing a substrate layer; forming a container having a bottom andsidewall from said substrate layer; depositing a thin first layer of abarrier layer metal covering at least said bottom and sidewall of saidcontainer; depositing a conductive material substantially completelyfilling said container; depositing a thin second layer of said barrierlayer metal encapsulating said conductive material in said container;and planarizing said thin second layer of said barrier layer metal. 13.The method of claim 12, further comprising removing said substrate layersurrounding said container to reveal an encapsulated conductive pillar.14. The method of claim 12, wherein said substrate layer includes aconductive plug, said conductive plug being located at said bottom ofsaid container contacting said first layer of said barrier layer metal.15. The method of claim 14, further comprising forming a layer of ahigh-dielectric constant material over at least said barrier metal. 16.The method of claim 15, further comprising forming a top electrode oversaid high-dielectric constant material to form a microelectroniccapacitor.
 17. The method of claim 12, wherein said substrate layer isselected from the group consisting of single component semiconductormaterials, compound semiconductor materials, ceramic single crystals,ceramic poly-crystals, metals, and amorphous/glassy materials.
 18. Themethod of claim 12, wherein said barrier layer metal is selected fromthe group consisting of platinum, palladium, ruthenium, iridium,rhodium, osmium, silver, gold, RuO₂, IrO₂, Rh₂O₃, OsO₂, and PdO₂. 19.The method of claim 12, wherein said conductive material is selectedfrom the group consisting of W, WSi_(x), Ru, RuOx, and Si₃N₄.
 20. Themethod of claim 14, wherein said conductive plug is selected from thegroup consisting of TiN, zirconium nitride, titanium silicide, tantalumsilicide, tungsten silicide, molybdenum silicide, nickel silicide,cobalt silicide, tantalum carbide, tantalum boride, polysilicon,germanium, W, Ta, Ti, Mo, TiW, boron carbide, and Cu.
 21. The method ofclaim 16, wherein said top electrode is platinum.
 22. The method ofclaim 12, wherein said depositing is by chemical vapor depositing (CVD).23. The method of claim 12, wherein said depositing is by sputtering.24. The method of claim 12, wherein said planarizing is performed bychemical mechanical planarization.
 25. The method of claim 12, whereinsaid first layer of the barrier metal is deposited to a thickness ofabout 200 Å.
 26. The method of claim 12, wherein said second layer ofthe barrier metal is deposited to a thickness of about 200 Å.
 27. Themethod of claim 12, wherein said container has a width ranging fromabout 1500 Å to about 2000 Å, and a height ranging from about 2000 Å toabout 30000 Å.
 28. The method of claim 13, wherein said removing isperformed by anisotropic etching.
 29. The method of claim 13, furthercomprising heat treating said pillar at an elevated temperature of about400° C. to about 900° C. for about 1 minute to 3 hours.
 30. The methodof claim 15, wherein said dielectric layer has a thickness of about 30Å.
 31. The method of claim 16, wherein said top electrode layer has athickness of about 500 Å.
 32. A method of forming an encapsulatedmicroelectronic structure suitable for use with a high-dielectricconstant material, the method comprising: providing a substrate layerhaving a surface; forming a container having a bottom and sidewall fromsaid substrate layer; depositing a thin first layer of a barrier layermetal covering said bottom and sidewall of said container and saidsurface of said substrate; depositing a conductive material coveringsaid first layer of a barrier layer metal and completely filling saidcontainer; removing a portion of said conductive material to expose anupper portion of said barrier layer metal provided on said sidewall ofsaid filled container; depositing a thin second layer of said barrierlayer metal encapsulating said conductive material in said container;and planarizing said thin second layer of said barrier layer metal. 33.The method of claim 32, wherein said removing is performed with an insitu, highly directional cleaning with a fluorinated cleaner.
 34. Themethod of claim 32, further comprising removing said substrate layersurrounding said container to reveal an encapsulated conductive pillar.35. The method of claim 34, further comprising the step of heat treatingsaid pilar at an elevated temperature of about 400° C. to about 900° C.for about 1 minute to 3 hours.
 36. The method of claim 34, wherein saidremoving is performed by anisotropic etching.
 37. The method of claim32, wherein said substrate layer includes a conductive plug, saidconductive plug being located at said bottom of said containercontacting said first layer of said barrier layer metal.
 38. The methodof claim 37, further comprising forming a layer of a high-dielectricconstant material over at least said barrier metal.
 39. The method ofclaim 38, further comprising forming a top electrode over saidhigh-dielectric constant material to form a microelectronic capacitor.40. The method of claim 39, wherein said substrate layer includes aconductive plug which contacts said first layer of said barrier layermetal.
 41. The method of claim 40, further comprising forming a layer ofa high-dielectric constant material over at least said pillar.
 42. Themethod of claim 41, further comprising forming a top electrode over atleast said high-dielectric constant material to form a microelectroniccapacitor.
 43. A method of forming a capacitor having an encapsulatedhigh-dielectric constant material, the method comprising: providing asubstrate layer having a conductive plug; forming a container having abottom and sidewall from said substrate layer, said conductive plugbeing located at said bottom of said container; depositing a thin firstlayer of a barrier layer metal covering said bottom and sidewall of saidcontainer in which said conductive plug contacts said first layer ofsaid barrier layer metal; depositing a conductive material substantiallycompletely filling said container; depositing a thin second layer ofsaid barrier layer metal encapsulating said conductive material in saidcontainer; planarizing said thin second layer of said barrier layermetal; forming a layer of a high-dielectric constant material over saidconductive material; and, forming a top electrode over saidhigh-dielectric constant material.
 44. A memory device having amicroelectronic structure, the microelectronic structure comprising: asubstrate layer; a thin barrier layer metal on said substrate layer; anda conductive material encapsulated by said thin barrier layer metal. 45.A memory device having a capacitor, the capacitor comprising: aninsulating substrate layer having a conductive plug; a thin barrierlayer metal on said insulating substrate layer over said conductiveplug; a conductive material encapsulated by said thin barrier layermetal; a dielectric layer provided over said barrier layer metal; and atop electrode layer provided over said dielectric layer.
 46. A computersystem, the computer system comprising a microelectronic device, thedevice including: a substrate layer; a thin barrier layer metal on saidsubstrate layer; and a conductive material encapsulated by said thinbarrier layer metal.
 47. A computer system, the computer systemcomprising a microelectronic device, the device including: an insulatingsubstrate layer having a conductive plug; a thin barrier layer metal onsaid insulating substrate layer over said conductive plug; a conductivematerial encapsulated by said thin barrier layer metal; a dielectriclayer provided over said barrier layer metal; and a top electrode layerprovided over said dielectric layer.